1. Field of the Invention
The present invention relates to the fields of Logic Design, Design for Testability and Scan Based Design. More specifically, the present invention is an inter-domain latch, which has particular application to implementing scan based design for multiple clock edge digital logic.
2. Background
Today, many digital logic designs incorporate some forms of scan based design for testability. Scan based designs can be classified as full serial integrated scan, isolated serial scan, or non-serial scan. The various forms of scan based design differs in the employment of shift register, and if used, its composition, and whether it is part of the normal data path.
However, the various forms of scan based design are all used for the purpose of increasing the controllability and observability of the logic design. Controllability is the ability to establish a specific signal at each node in the logic design by setting values on the logic's input. Observability is the ability to determine the signal value at any node in the logic design by controlling the logic's input and observing its output.
As a result of enhanced controllability and/or observability, higher fault coverage of the logic design can be achieved. Fault coverage is the ratio between the number of faults detectable and the total number of faults in the assumed fault universe. Thus, controllability and observability are the key measures of testability. The goal is to achieve 100% controllability and 100% observability if possible.
When applying scan based design principles to sequential logic designs, all storage elements (flip-flops) are made scannable, and have a common clock applied to them. As a result, the entire sequential logic design is transformed into a combinatorial logic design, thereby allowing test patterns to be easily generated for the sequential logic design. For further information, see E.G. McCluskey, Logic Design Principles, Prentice Hall, 1986.
However, for more complex logic designs, sometimes it becomes necessary to use flip-flops clocked with two clocks, one being the complement of the other. In other words, the logic design includes rising edge as well as falling edge flip-flops. In order to implement scan based design for these more complex logic designs, typically the logic design is partitioned into a number of domains (also known as partitions), with each domain being affected by either the rising or the falling clock edge, and additional logics are placed on the boundaries connecting the various domains. Each domain is then treated as a separate independent scannable entity for testing.
The only issue remains to be resolved is how to handle the signal interface between two domains. A signal entering from one domain to another domain having opposite edge clocks for their flip-flops is an unobservable signal for the originating domain and an uncontrollable signal for the receiving domain. The interface signals between two domains having opposite edge clocks for their flip-flops are categorized in FIGS. 1a-1b.
FIG. 1a illustrates the four cases where the signal goes from a rising edge domain to a falling edge domain, and FIG. 1b illustrates the four cases where the signal goes from a falling edge domain to a rising edge domain. With each group of four cases, there are two cases where intervening logics are not involved, cases Ia and Ib of FIG. 1a, or cases IIIa and IIIb of FIG. 1b, and there are two cases where intervening logics are involved, cases IIa and IIb of FIG. 1a, or cases IVa and IVb of FIG. 1b. With each group of two cases, there is a first case where an intervening latch is not involved, cases la or IIa of FIG. 1a, or cases IIIa or IVa of FIG. 1b, and there is a second case where an intervening latch is involved, cases Ib or IIb of FIG. 1a, or cases IIIb or IVb of FIG. 1b.
FIGS. 2a-2b illustrate how a controllable and observable point can be established at the boundary of the two domains for four of the eight cases. FIG. 2a illustrates for cases Ia and IIa of FIG. 1a, and FIG. 2b illustrates for cases Ilia and IVa of FIG. 1b. In each case, the four latches that form the rising edge and falling edge flip-flops, 12a and 14a, 12c and 14c, 12e and 14e, or 12g and 14g, operate in three phases of a common clock, thus, a "redundant" latch exists. Therefore, a controllable and observable point at the boundary of the two domains can easily be established by adding a rising edge flip-flop, 26a or 26b, for cases Ia and IIa, or a falling edge flip-flop, 30a or 30b, for cases IIIa and IVa, in the first domain (D1) 10, and adding a multiplexor, 28a-28d, in the second domain (D2) 20, for each of the four cases. In each case, the added multiplexor, 28a-28d, is coupled to a controllable input. As a result the output signal of domain one (D1) 10 is observable through the added rising edge or falling edge flip-flop, 26a, 26b, 30a, or 30b, and the input signal to domain two (D2) 20 is controllable through the added multiplexor, 28a, 28b, 28c or 28d.
FIGS. 3a-3b illustrate how a controllable and observable point can be established at the boundary of the two domains for the remaining four cases. FIG. 3a illustrates for cases Ib and IIb of FIG. 1a, and FIG. 2b illustrates for cases IIIb and IVb of FIG. 1b. In each case, the four latches that form the rising edge and falling edge flip-flops, 12b and 14b, 12d and 14d, 12f and 14f, or 12h and 14h, are fully utilized, no "redundant" latch exists. Therefore, a controllable and observable point at the boundary of the two domains can not be established as easily as before. However, it can still be established by adding a rising edge flip-flop, 26c or 26d, for cases Ib and IIb, or a falling edge flip-flop, 30e or 30f, for cases IIIb and IVb, in the first domain (D1) 10, and adding a multiplexor, 28e or 28f, and a falling edge flip-flop, 30c or 30d, for cases Ib and IIb, and a multiplexor, 28g or 28h, and a rising edge flip-flop, 26e or 26f, for cases IIIb and IVb, in the second domain (D2) 20. In each case, the added multiplexor, 28e-28h, is coupled to a controllable input through the added falling edge or rising edge flip-flop, 30c, 30d, 26e or 26f. As a result the output signal of domain one (D1) 10 is observable through the added dosing edge or falling edge flip-flop, 26c, 26d, 30e, or 30f, and the input signal to domain two (D2) 20 is controllable through the added multiplexor, 28e, 28f, 28g or 28h, and its corresponding falling edge or rising edge flip-flop, 30c, 30d, 26e or 26f.
Thus, for cases Ib, IIb of FIG. 1a, and cases IIIb and IVb of FIG. 1b, one rising edge flip-flop, one falling edge flip-flop and one multiplexor are additionally required to establish a controllable and observable boundary point between the two domains where only a functional latch exists. To have all functional latches in the designs illustrated in cases Ib and IIb of FIG. 1a and cases IIIb and IVb of FIG. 1b replaced by a latch, two additional flip-flops and a multiplexor is a large increase in hardware requirement.
Therefore, it is desirable to provide a method and apparatus for establishing a controllable and observable boundary point between two domains with reduced amount of hardware requirements. As will be disclosed, this object and desired result are among the objects and desired results of the present invention, which provides an inter-domain latch having relatively low hardware requirement, that can be used to establish a controllable and observable boundary point between two domains with opposite edge clocks for their flip flops.